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1 standard products UT54ACS299E cmos 8-bit universal shift/storage register with three-state outputs datasheet july 2, 2013 www.aeroflex.com/logic features ? common parallel i/o for reduced pin count ? additional serial inputs and outputs for expansion ? three-state outputs for bus-oriented applications ? operate with outputs enabled or at high impedance ? four operating modes: shift left, shift right, load and store ? can be cascaded for n-bit word lengths ? 0.6 ? m commercial radhard tm cmos - total dose: 100k rad(si) - single event latchup immune - seu onset let: 95 mev-cm 2 /mg (4.5v) and 48mev-cm 2 /mg (3.0v) ? applications: - stacked or push-down registers - buffer storage - accumulator registers ? output source/sink 24ma ? available qml q or v processes ?? standard microcircuit drawing 5962-06238 ? package: - 20-lead flatpack description the UT54ACS299E 8-bit shift/storage register is built using aeroflex?s commercial radhard tm epitaxial cmos technolo- gy and is ideal for space appli cations. the ut54 acs299e is an 8-bit universal shift/storage register featuring multiplexed i/o ports to achieve full 8-bit data handling in a single 20-pin pack- age. two function-select (s0, s1) inputs and two output enable (oe1 , oe2 ) inputs can be used to choose the mode of operation listed in the function table. additional outputs are provided for flip flops q0, q7 to allow easy serial cascading. a separate active low master reset (mr ) is used to reset the register, over- riding the select and cp inputs. all flip-flops are brought out through three-state buffers to separate i/o pins that also serve as data inputs in the parallel load mode. all other state changes are initiated by the rising edge of the clock. logic symbol pin description pin names description cp clock pulse input ds0 serial data input for right shift ds7 serial data input for left shift s0, s1 mode select inputs mr asynchronous master reset oe1 , oe2 three-state output enable inputs io0-io7 parallel data inputs or three-state parallel out- puts q0, q7 serial outputs mr oe1 r 6, 13 i01 i03 i04 i05 i06 ds7 q7 i07 i02 3, 4d 12, 13 2, 4d z12 3, 4d z6 i00 5, 13 3, 4d 1, 4d ds0 z5 q0 oe2 & s0 s1 cp srg8 3 en13 0 1 c4/1 /2 m 0 3 (9) (2) (3) (19) (12) (1) (6) (14) (5) (4) (16) (15) (18) (17) (8) (11) (7) (13)
2 function table pinouts inputs operation mr s1 s0 cp oe 1 oe 2 l x l x l l q0=q7=low, async reset l l x x l l q0=q7=low, async reset l h h x x x q0=q7=low, i/o = hiz, async reset h h h ? x x parallel load; ion > qn h l h ? l l shift right; ds0 > q0,q0 > q1, etc. h ? l ? l l shift left; ds7 > q7, q7 > q6, etc. h l l x l l hold 1 2 3 4 5 7 6 20 19 18 17 16 14 15 s0 oe 1 oe 2 io6 io4 io2 io0 v dd s1 ds7 q7 io7 io3 8 13 q0 io1 io5 9 12 mr cp 10 11 v ss ds0 20-lead flatpack top view
3 logic diagram cp d q c d cp d q c d cp d q c d cp d q c d cp d q c d cp d q c d cp d q c d cp d q c d io7 io6 io5 io4 io3 i02 io1 io0 oe2 oe1 s0 s1 mr cp ds0 q7 ds7 q0
4 operational environment 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table. 2. adam?s 90% worst case particle environment, geosynchronous orbit, 100 mils aluminum shielding. 3. not tested, inherent of cmos technology. absolute maximum ratings 1 note: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the opera tional sections is not recommend ed. exposure to absolute maxi mum rating conditio ns for extended periods may affect device reliability and performance. recommended operating conditions parameter limit units total dose 1.0e5 rad(si) sel immune >108 mev-cm 2 /mg seu onset let - 3.0v seu onset let - 4.5v 48 95 mev-cm 2 /mg seu error rate - 3.0v 2 seu error rate - 4.5v 2 1.4e-8 8.1e-10 errors/device-day neutron fluence 3 1.0e14 n/cm 2 symbol parameter limit (mil only) units v i/o voltage any pin during operation -.3 to v dd +.3 v v dd supply voltage -0.3 to 7.0 v t stg storage temperature range -65 to +150 ? c t j maximum junction temperature +175 ? c ? jc thermal resistance junction to case 20 ? c/w i i dc input current ? 10 ma p d maximum power dissipation 200 mw symbol parameter limit units v dd supply voltage 3.0 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 ? c t inrise t infall maximum input rise or fall time (v in transitioning between v il (max) and v ih (min)) 20 ns
5 dc electrical characteristics 1 ( -55 ? c < t c < +125 ? c) symbol parameter condition min max unit v il low level input voltage 2 v dd from 3.0v to 5.5v 0.3 v dd v v ih high level input voltage 2 v dd from 3.0v to 5.5v 0.7 v dd v i in input leakage current v dd from 3.0v to 5.5v v in = v dd or v ss -1 1 ? a i oz three-state output leakage current v dd from 3.0v to 5.5v v in = v dd or v ss -10 10 ? a i os short-circuit output current 4, 5 v o = v dd or v ss v dd from 3.0v to 5.5v -600 600 ma v ol1 low-level output voltage 6 i ol = 12ma i ol = 100 ? a v dd = 3.0v to 3.6v v in = 0.7v dd or 0.3v dd 0.4 0.2 v v ol2 low-level output voltage 6 i ol = 24ma -55 ? c, 25 ? c i ol = 24ma +125 ? c i ol = 100 ? a v dd = 4.5v to 5.5v v in = 0.7v dd or 0.3v dd 0.36 0.5 0.2 v v ol3 low-level output voltage 6, 7 i ol = 50ma -55 ? c, 25 ? c v dd = 5.5v +125 ? c v in = 0.7v dd or 0.3v dd 0.8 1.0 v v oh1 high-level output voltage 6 i oh = -12ma i oh = -100 ? a v dd = 3.0v to 3.6v v in = 0.7v dd or 0.3v dd v dd - 0.6 v dd - 0.2 v v oh2 high-level output voltage 6 i oh = -24ma -55 ? c, 25 ? c i oh = -24ma +125 ? c i oh = -100 ? a v dd = 4.5v to 5.5v v in = 0.7v dd or 0.3v dd v dd - 0.64 v dd - 0.8 v dd - 0.2 v
6 notes: 1. all specifications valid for radiation dose ? 1e5 rad(si) per mil-std-883, method 1019. 2. functional tests are conducted in accordance with mil-std-883 with the followi ng input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any inpu t voltage within the above specified range, but are guaranteed to v ih (min) and v il (max). 3. guaranteed by characterization. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. supplied as a design limit, but not guaranteed or tested. 6. per mil-prf-38535, for current density ? 5.0e5 amps/cm 2 , the maximum product of load capac itance (per output buff er) times frequency should not exceed 3,765 pf-mhz. 7. transmission driving tests are performed at v dd = 5.5v, only one output loaded at a ti me with a duration not to exceed 2ms. the test is guaranteed, if not tested, for v in =v ih minimum or v il maximum. 8. power does not include power contribu tion of any cmos output sink current. 9. power dissipation specified per switching output. 10.capacitance measured for initial qualification and when design changes may affect the value. capac itance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. . v oh3 high-level output voltage 6, 7 i oh = -50ma -55 ? c, 25 ? c v dd = 5.5v +125 ? c v in = 0.7*v dd or 0.3*v dd v dd - 1.1 v dd - 1.25 v v ic + positive input clamp voltage for input under test, i in = 18ma v dd = 0.0v 0.4 1.5 v v ic - negative input clamp voltage for input under test, i in = -18ma v dd = open -1.5 -0.4 v p total power dissipation 3, 8, 9 c l = 20pf v dd from 3.0v to 5.5v 0.5 mw/ mhz i ddq standby supply current v dd pre-rad 25 o c pre-rad -55 o c to +125 o c post-rad 25 o c v in = v dd or v ss, v dd = 5.5 oe n = v dd oe n = v dd oe n = v dd 10 80 ? a ? a c in input capacitance 10 ? = 1mhz @ 0v v dd from 3.0v to 5.5v 17 pf c out output capacitance 10 ? = 1mhz @ 0v v dd from 3.0v to 5.5v 17 pf
7 test load or equivalent 1 v dd 40pf 100ohms v dd 100ohms notes: 1. equivalent test circuit means that du t performance will be co rrelated and remain guaranteed to the applicable test circuit, above, whenever a test platform change necessitates a deviation fro m the applicable test circuit.
8 ac electrical characteristics 1 (3.3 volt operation) (v dd = 3.3v ? 0.3v, -55 ? c < t c < +125 ? c) notes: 1. all specifications valid for radiation dose ? 1e5 rad(si) per mil-std-883, method 1019. 2. verified by at speed functional test. symbol parameter min max unit t plh1 propagation delay cp to q0 or q7 (shift left or right) 4.5 10.5 ns t phl1 propagation delay cp to q0 or q7 (shift left or right) 4.5 10.5 ns t plh2 propagation delay cp to ion 5 14 ns t phl2 propagation delay cp to ion 5 14 ns t phl3 propagation delay mr to q0 or q7 6 11 ns t phl4 propagation delay mr to ion 7 15.5 ns t pzl output enable time oe to ion 4 10.5 ns t pzh output enable time oe to ion 4 10.5 ns t plz output disable time oe to ion 3 6.5 ns t phz output disable time oe to ion 3 6.5 ns t w1 2 pulse width cp 5.5 ns t w2 2 pulse width mr 5.5 ns t s1 setup time; high or low; sn to cp 3 ns t h1 hold time; high or low; sn to cp 0.5 ns t s2 setup time; high or low; dsn to cp 1 ns t h2 hold time; high or low; dsn to cp 0.5 ns t s3 setup time; high or low; ion to cp 1.5 ns t h3 hold time; high or low; ion to cp 0.5 ns t rec recovery time mr to cp 1 ns f max 2 maximum frequency cp 70 mhz
9 t plz t pzh t pzl t phz oe n 3v output normally low enable disable times 3v output normally high v dd v dd /2 0v v dd /2 v dd /2 .8v dd .2v dd v dd /2+0.2 v dd /2-0.2 .2v dd + .2v .8v dd - .2v propagation delay cp output t phl1,2 t plh1,2 v oh v ol v dd /2 v dd v dd /2 0v setup and hold measurements sn or dsn or ion v dd v dd /2 0.0v cp input v dd v dd/2 0.0v t s1,2,3 t h1,2,3 t w1 t w2 t rec mr t phl3 t phl4 data outputs q0, q7, io<0:7> v dd v dd /2 0.0v v oh v dd /2 v ol
10 ac electrical characteristics 1 (5 volt operation) (v dd = 5v ?? 10%, -55 ? c < t c < +125 ? c) notes: 1. all specifications valid for radiation dose ? 1e5 rad(si) per mil-std-883, method 1019. 2. verified by at speed functional test. symbol parameter min max unit t plh1 propagation delay cp to q0 or q7 (shift left or right) 4 8 ns t phl1 propagation delay cp to q0 or q7 (shift left or right) 4 8 ns t plh2 propagation delay cp to ion 4.5 9 ns t phl2 propagation delay cp to ion 4.5 9 ns t phl3 propagation delay mr to q0 or q7 59ns t phl4 propagation delay mr to ion 5.5 11 ns t pzl output enable time oe to ion 3 7 ns t pzh output enable time oe to ion 3 7 ns t plz output disable time oe to ion 3 6 ns t phz output disable time oe to ion 3 6 ns t w1 2 pulse width cp 5 ns t w2 2 pulse width mr 5ns t s1 setup time; high or low; sn to cp 2 ns t h1 hold time; high or low; sn to cp 0.5 ns t s2 setup time; high or low; dsn to cp 1 ns t h2 hold time; high or low; dsn to cp .5 ns t s3 setup time; high or low; ion to cp 1 ns t h3 hold time; high or low; ion to cp 0.5 ns t rec recovery time mr to cp 0.5 ns f max 2 maximum frequency cp 90 mhz
11 t plz t pzh t pzl t phz oe n 5v output normally low enable disable times 5v output normally high v dd v dd /2 0v v dd /2 v dd /2 .8v dd .2v dd v dd /2+0.2 v dd /2-0.2 .2v dd + .2v .8v dd - .2v propagation delay cp output t phl1,2 t plh1,2 v oh v ol v dd /2 v dd v dd /2 0v setup and hold measurements sn or dsn or ion v dd v dd /2 0.0v cp input v dd v dd/2 0.0v t s1,2,3 t h1,2,3 t w1 t w2 t rec mr t phl3 t phl4 data outputs q0, q7, io<0:7> v dd v dd /2 0.0v v oh v dd /2 v ol
12 package note: 1. seal ring is connected to v ss . 2. units are in inches. 3. all exposed metalized areas must be gold plated 100 to 225 microinches thick and all bottom side exposed metalized areas must be gold plated to 60 microinche s thick nominal. both sides shall be over electroplated nickel undercoating 100 to 350 microinches per mil-prf-38535. figure 1. 20-lead flatpack
13 ordering information UT54ACS299E: smd lead finish: (notes 1 & 2) (a) = hot solder dip (c) = gold (x) = factory option (gold or solder) case outline: (x) = 20 lead bb fp class designator: (q) = class q (v) = class v device type (01) = 8-bit universal shift/storage register (3.0v - 5.5v) drawing number: 06238 total dose: (note 3) (r) = 1e5 rad(si) federal stock class designator: no options 5962 r 06238 ** * * * notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be eith er ?a? (solder) or ?c? (gold). 3.total dose radiation must be specified when ordering. qml q no t available without radiation hardening. qml q and qml v not a vailable without radiation hardening. for prototyping inquiries, contact factory.
14 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc., reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a pr oduct or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. aeroflex colorado spring s - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hirel

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